FIR Filter Design and Motion Estimation Algorithms on Pipelined Configurable Gate Array (PiCoGA)

Abstract

Reconfigurable processors are an appealing option to achieve high performance and low energy consumption in digital signal processing, but their utilization often involves hardware issues not usual for algorithm developers proficient in high level languages. This project thesis presents a Griffy C-based algorithm development flow for XiRisc, a reconfigurable processor architecture targeted at embedded systems, that couples a VLIW rise core with a custom designed programmable hardware unit optimized for being programmed starting from Data Flow Graph (DFG) descriptions. Starting from Griffy C-language, the flow produces both executable code for the processor core and configuration bits for the embedded programmable unit used here is PiCoGA (Pipelined Configurable Gate Array). It supports various applications and works well for signal processing and communications applications. In my thesis work, I carryout the designs like FIR filter design and some of the Motion estimation algorithms on PiCoGA and checked various test cases for those designs.