Design of Low Noise Amplifier Using Sub-Micron Technology

Abstract

A design methodology of Differential Design to work over the Bluetooth frequency, CMOS low noise amplifier (LNA) with source degeneration is presented. The results show that the proposed topology is effective. To validate these design concepts, this LNA was realized in 0.18μm CMOS technology using Virtuoso Tool from Cadence. The measured noise figure is 3 dB and the gain is 21.6 dB.

The objectives established at the outset of the project are:

i) To develop a circuit topology and to size all circuit components to meet specifications, to build the LNA using 0.18 μm CMOS technology ii) To gain experience working with Cadence software and the various types of analysis, including s-parameter and periodic steady-state analysis iii) To simulate the LNA operation in Cadence to generate gain, s-parameters, noise, and stability results.

Different parameters were calculated for the design and implemented to meet the intended specifications. The dependencies of various parameters on result have been analyzed and had been included in the thesis. Results for different values of inductors used in the circuit have been analyzed and also their effect on Noise Figure, Gain and s-Parameters are shown.