Development of Capacitance Extraction Methodology for IO Cells

Abstract

Gate capacitance has complex voltage dependency on terminal voltages but the impact of this voltage dependency of gate capacitance on power and delay has not been fully investigated, especially, in low-voltage, low-power designs. Introducing an effective gate capacitance, CGeff, it is shown that the power and delay of CMOS digital circuit can be estimated accurately. CGeff is a strong function of VTH/VDD and VTH/VDD tends to increase in low-voltage region. Hence, the effective capacitance relative to oxide capacitance, COX, is decreasing in low-voltage, low-power designs. Therefore, considering CGeff, in accurate power and delay estimation becomes more important in the future. For different cells the methodology to extract the gate capacitance depends on the nets connected to the pin to be analyzed and the devices on these nets. The current capacitance extraction methodology is studied and it is found that some correction is required to take in to account the leakage at the pins. Future scope of this project work will be to specify a methodology, which can be a mere modification in the current one, that extracts the gate capacitance with certain level of accuracy considering the leakages involved at the pins.