High Speed BIST Architecture for Embedded SRAM

Abstract

Embedded memories consume a major portion of the die area in deep submicron systems-on-a-chip (SOCs). Manufacturing test of embedded memories is an important step in SCO production process that screens out the defective chips. Built-in self-test (BIST) is establishing itself as an enabling technology that can effectively tackle the SOC test problem. However, unless consciously implemented, its main limitations lie in area overhead and potential performance penalty. But the advantage gain is decrease in testing time for chip.

During First phase of this dissertation, detailed analysis and some implementation of shared BIST have been done. In this shared BIST there is one master controller and wrappers around different memories. Master controller control the operation of different wrapper of different type of memory groups. Here the memory can be of any type, like means Single Port RAM, Dual Port RAM, and ROM. In this architecture to overcome routing congestion created by the connection between controller and wrappers, interface between controller and wrapper is made serial. Master controller program the different wrapper through this serial link, and take different results from this serial link. The first phase of thesis mainly deals with study and development of this shared BIST architecture. Here development refers to adding some feature to already developed architecture, feature like fail counter, serial access mode, and validation of this whole architecture.

During second phase of this dissertation, work is done on development BIST for high speed Dual Port RAM. The embedded dual ported SRAM plays a critical role in today ASIC to match the data rate across multiple clock domains. A typical dual ported SRAM application could be a mailbox to pass critical data, to synchronize asynchronous operations, or to provide buffers between slow interfaces to faster embedded processors.

These operations access both ports independently without writing at the same address. Because of both ports has read and write capabilities there is complex coupling faults can happen in dual port SRAM which are not present in normal single port SRAMs. The main work in this project is development of mask algorithm, redundancy engine for BIST; the other thing that has to see during this development is the run BIST at speed of memory, which is around the 1 GHz. Also to add address decoder test in BIST.

The second phase of this dissertation, mainly deal with development of high speed BIST architecture with new mask test and redundancy engine, implementation and validation of this high speed architecture.