DDR3 Crosstalk Cancellation Circuit

Abstract

In submicron designs, the chip size results in coupling capacitance and intercon-nect delay due to increase in integration density, the closer proximity of the adjacentwires on the same layer and the high aspect ratio. Currently, cross-coupling capac-itance dominates the inter-layer capacitance with every new process technology, be-cause the wires are getting much closer to each other. Most of the potential problems,such as crosstalk is related to the signal propagation and/or high currents throughthe metal wires. Signal integrity includes all IC design eects that cause the designto malfunction due to the distortion of the signal waveform.Crosstalk is the detrimental phenomenon by which a signal sent on one of thetransmission channels produces noise on other transmission channels. Crosstalk anal-ysis determines the noise induced on a net (the victim) by its switching neighboringnets (the aggressors). DDR3 is the third generation of Double Data Rate SDRAMmemory technologies providing more features and higher performance in terms ofhigher speed, higher bandwidth, lower power consumption and heat dissipation.In this project, the transmitter and receiver circuits employ the industry standardDDR3 protocol. A typical signaling system consists of a transmitter, a channel,and a receiver. For the baseline simulations, standalone schematic capture and thesimulations of the transmitter, receiver and of the single channel have been done.Thecrosstalk impacted eye and non-crosstalk impacted eye results shows the eect on thevictim by the aggressor nets. The nal ODCC will require two sub-circuits, in whichone is at the transmission side and one is at the receiver side which in whole nallyimproves the crosstalk aected eye and mitigate the eect of crosstalk.