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Title: | Design & Simulation of Low Power High Speed CMOS Comparator in Deep Sub-micron Technology |
Authors: | Gandhi, Priyeshkumar Pratapbhai |
Keywords: | EC 2008 Project Report 2008 EC Project Report Project Report EC (VLSI) 08MEC 08MEC004 VLSI VLSI 2008 |
Issue Date: | 1-Jun-2010 |
Publisher: | Institute of Technology |
Series/Report no.: | 08MEC004 |
Abstract: | In today's world, where demand for portable battery operated devices is increas- ing, a major thrust is given towards low power methodologies for high resolution and high speed applications. In this high speed low power, low voltage era there is an in- creasing demand of a High speed Comparator for ADC, DAC and various applications in a analog and digital domain. High speed applications and technology is becoming an increasingly important and growing area of electronics. Comparator is the main building block in ADC architecture. Main purpose of the comparator is to compare a signal with a reference signal and produce an output depending on whether the input signal is greater or smaller than reference. A new fully di erential CMOS dynamic comparator using positive feedback suit- able for pipeline A/D converters with low power dissipation, low o set, low noise and high speed is presented here. Inputs are recon gured from typical di erential pair comparator such that near equal current distribution in the input transistors can be achieved for a meta stable point of the comparator. Restricted signal swing clock for the tail current is also used to ensure constant currents in the di erential pairs. Less than 10mV o set voltage is easily achieved with the proposed structure making it favorable for ash and pipeline data conversion applications. The topology presented here is based on two cross coupled di erential pairs pos- itive feedback and switchable current sources, has a small power dissipation, less area, and it is shown to be very robust against transistor mismatch, noise immunity. Comparators is designed in TSMC 0.35 m Technology with 2V power supply for Preampli er Based Comparator and 1:8V for Dynamic Comparators . Comparative Analysis is done for the di erent topologies of the Comparator Designs. The Pre layout Simulations and Post layout Simulations are done using Eldo Spice Tool and Layout is made using Mentor Graphics Back End Design Tools like IC Station and DA-IC (Design Architect). |
URI: | http://hdl.handle.net/123456789/1547 |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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08MEC004.pdf | 08MEC004 | 5.07 MB | Adobe PDF | ![]() View/Open |
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