Power verification of multi-power domain SOC

Abstract

In last few decades, the demand of portable devices such as laptop, palmtop and cell phones is increased drastically. These devices use low supply voltages using single cell battery. Research in integrated circuits has recently gone in the direction of low- power (LP) techniques especially in the environment of portable systems. For battery- powered devices, which comprise one of the fastest growing segments of the electronics market, the leakage current in deep submicron processes is a major problem. To combat this problem, designers are using aggressive approaches at every stage of the design process, from software to architecture to implementation. These approaches include power gating, where blocks are powered down when not in use, and multi- threshold libraries that can trade-o leakage current for speed. For all applications, the total power consumption of complex SoCs presents a challenge. To address this challenge, designers are moving from a monolithic approach for power the chip, where a single supply voltage is used for all the non-IO gates of the design to a multiple supply architecture, where di erent blocks run at di erent voltages, depending on their individual requirements. In some cases, designers are using voltage scaling techniques to change the supply voltage in a critical block depending on its workload and hence required performance. This project is done to verify, visualize and analyze the voltage and power domain management in a SoC. This includes validating all the port signals of the di erent power domains are power gated correctly. Signals which are crossing between di erent voltage domains with di erent supply voltages are level shifted appropriately. All the cells with a given hierarchy should be connected to proper supply including all the special cells like power-switch, level-shifters and Always-on cells etc. This validation is done by using the Atrenta's spyglass low power tool. This validation is done on di erent stages of the design like RTL, Pre-layout netlist and Post- Layout netlist.