Design and Implementation of Discrete Cosine Transform Architecture Blocks

Abstract

The project assigned is “Design & Implementation of Discrete Cosine Transform Architecture Blocks” for various Image Processing and Image Compression applications. This project aims at efficient implementation of 2-D 8 x 8 DCT architecture block. The Discrete Cosine Transform (DCT) has been widely recognized as the most effective technique among various transform-coding methods for image and video signal compression as its basis images are fixed. A single chip implementation of the two-dimensional (2-D) DCT will drastically reduce the cost and the speed of image compression systems. In this project, the implementation of 2-D 8 x 8 DCT block using a concurrent architecture is presented. The block contains 16 processing elements working in parallel. High speed and high throughput is achieved through bit-serial and bit-parallel architecture along with pipelining. Multiplier accumulators in the DCT architecture have been designed with Distributed Arithmetic. Distributed Arithmetic offers reduction in silicon area by, eliminating the parallel multipliers. Furthermore, a very high-speed operation can be achieved because the critical path is formed in adders instead of multipliers. In the multiply-accumulate operations based on distributed arithmetic, pre-calculated partial products are read out from ROM’s and accumulated in a bit-wise manner from the LSB’s to the MSB’s. The rounding circuits and limiters are inserted to the output portions of the DCT processing units so as to prevent the overflow and underflow. The structure is highly regular and modular, thus very efficient for FPGA implementation. The 1-D 8-point DCT block accepts 8-bit input, maintains 12 bits after the 2-D DCT. Power reduction schemes are also used. Introduction of Most Significant Bit Rejection Ratio reduces the power consumption by 40-50 percent. Latency of the system is 92 clocks. DCT is applied through core on different test images.