Optimizing ASIC Design Cycle Time

Abstract

Design veri cation is one of the most challenging tasks in hardware development. With the ever increasing complexity of digital systems, veri cation has become the primary bottleneck in circuit design, consuming up to 70 This thesis addresses the veri cation problem using a uni ed approach, which utilizes new mechanisms to bridge the gap between abstraction levels. The goal is to reduce the time spent on veri cation while increasing the test-bench quality. The rst mechanism is to develop combined veri cation environment between Matlab/Simulink and System verilog. The goal of such environment is to bridge the abstraction gap that exists between the algorithmic level and the lower levels. By providing a con gurable communication link between Matlab/Simulink and System Verilog, it is now possible to reuse high abstraction level models to verify system-level and register transfer-level representations. The time spent on test bench development is considerably reduced by reusing Matlab's data generators and data analysis mod- ules. The pre-veri ed blocksets library in Matlab dramatically increases the quality and the e ciency of the test bench. Moreover, when we go for co-simulation it opens up a wide range of visualization and data analysis capabilities to the System Verilog simulation. Experiments on Case-Study of Fixed point IIR lter have shown that such approach between Matlab and System Verilog provides 2/3rd order of percent- age speedup for test bench development and enables veri cation strategies that were simply not possible before. Secondly, we present a generalized version of transactor using Veri cation manual methodology called VMM for Transaction-level Modeling. Such a use of VMM will provides modularity necessary for reuse and migration across abstraction levels and projects. We demonstrate the capabilities and e ciency of Transaction level modeling through veri cation of Fixed point IIR lter These two mechanisms are compared with the traditional method of veri cation using only HVL such as system verilog. This foundation promotes early veri cation vii and vertical test bench reuse across abstraction levels. The veri cation platform that we have developed using Matlab and System Verilog combination in this thesis has proven to be a valuable addition to the range of methods already available to reduce veri cation time.