Design and Analysis of Special Purpose Library Approach

Abstract

A new category of devices -Structured ASICs are increasingly becoming available to ll in the gap of the programmability spectrum, which consists of FPGAs at one end and the standard cell ASICs at the other end. Structured ASICs have adopted best features of FPGAs and standard cell ASICs. They are closer to FPGAs in terms of low NRE cost and lesser turnaround design times, and closer to ASICs in terms of low power and high performance. This report addresses issues related to development and optimization of CMOS structured ASIC libraries. Challenges and problems related to development of 65nm technology library are greater compared to 45nm technology library. Since technologies are rapidly changing, the cell library has to be developed from scratch more frequently. Building of these high performance cell libraries not only reduces time and cost of generation and maintenance adequately (enabling new technologies to adopt quickly) but reduces design cycle greatly. This report also addresses the DFM methodologies and techniques and optimization of circuits.