Modeling of Devices and Design of Circuits in Emerging Technologies - FinFET and OTFT

Abstract

In the era of nanotechnology, it is very much essential to design high performance devices withvery low leakage, which can be operated at low voltage and fast response time along with theconsideration of commercial aspects such as cost and time-to-market etc. The use of planar bulkCMOS technology below 45 nm is rapidly losing its platform for realization of efcient analogand mixed mode circuits due to pronounced short channel effects, which cause major deviationfrom the desired performance. Therefore, it is of utmost importance to explore new technologieswith the help of the innovation in the eld of material science, fabrication techniques and TCADtools.Among the recent emerging technologies, FinFET and other Multi-Gate devices are mostpromising structures. FinFET devices show the excellent gate control over the channel whichresults in the reduced short channel effects (SCEs) and leakage current. FinFET based circuitdesigns become very much attractive especially below 45 nm regime for various analog andmixed signal circuits. FinFET being a non-planar device, the physical model development isa very complex and challenging task and needs 3-dimensional approach, therefore, it is stillunder investigation. Therefore, a novel look-up-table (LUT) technique is employed in designingvarious benchmark circuits using an Automatic Circuit Design Tool based on recent PSO(Particle Swarm Optimization) algorithm. This work initiates the efforts of comparing FinFETand bulk-planar MOSFET based various circuit performances for 45 nm nodes across the PVT(process, temperature, voltage) variations. FinFET shows the best performance especially foranalog circuit designs across all the PVT variations.The automatic circuit design platform utilizes the look-up table data generated using SANTAURUSTCAD simulator in 45 nm FinFET technology with minimum effective channel lengthof 20 nm for designing FinFET based benchmark circuits. The planar MOSFET based benchmarkcircuits are designed with the PTM (Predictive Technology Model) for all process cornersat 45 nm technology node and simulated using the NGSpice circuit simulator.iiOTFT (Organic Thin Film Transistor) devices are becoming more attractive with entirelydifferent dimensions in terms of the size, active material introduction, applications, ease of fabricationprocess, low cost and time-to-market etc. As per the prediction, OTFT is expectedto capture very large market in next ten years span with various applications like RFID, exibledisplays, smart biosensors, and smart fabrics, which can be fabricated on the various basematerials like plastic, cloth and glass. However, the compact models of OTFT are still under developmentand commercially not available. This project work is just for to reach an inch closertowards the development of an accurate macro-model for OTFT devices, considering the factthat these devices are with the shorter life-time, lesser stability and repeatability. The developedmodel shows the very good agreement with the measured data of ve different OTFT devicesof different channel lengths. The parameter extraction is done using the Parameter ExtractionTool based on the PSO algorithm has shown. Apart from the available data of OTFT devices,we have fabricated OTFT devices with different dimensions (W; L; tox), architectures (TCBGand BCBG), and active organic semiconductor compounds (P3HT and Pentacene).