Implementation of Error detecting and Error correcting Algorithm

Abstract

As SRAM and DRAM devices are scaled down, the number of variation-induceddefective memory cells increases rapidly. Combination of ECC, particularly SECDED,with a redundancy technique can eectively tolerate a high number of defects. WhileSECDED can repair a defective cell in a block, the block becomes vulnerable to softerrors.Error correcting codes have been successfully employed to correct errors associatedwith failures in computer memories. A typical code which has found wide applicationis the binary Hamming code. This code corrects single bit errors. With the advent oflarge-scale integration (LSI) storage array technology, the likelihood of errors whichexceed the correction and detection capability of such a code is signicant.The eectiveness of single error correcting, double error detecting (SECDED)memory relies on the assumption that most errors will involve only a single bit. Somestudies indicate that approximately 98% of al memory errors are single bit errors.SEC-DED memory requires 7 extra bits in a 32-bit wide memory system, but only8 extra bits in a 64-bit wide memory system. Error correcting memory is typicallyslower than non correcting memory due to the error correcting circuitry. Advantageto error correcting codes is that the system can monitor the rate at which correctableerrors occur, and a marginal part can be replaced before uncorrectable errors occur.This report content implementation of SECDED Algorithm (Hamming base andmin-odd weight base) in front-end and back-end. For front-end I used Xilinx andModelsim for front-end simulation. In Back-end design content full custom design ofmin odd weight SECDED algorithms, for that I have used Intel tool and analysis ofback-end design content performance, layout area and power dissipation simulation.