PSS Placer Tool for PiCoGA approach

Abstract

With recent advances in silicon device technology, Field-Programmable Gate Ar- rays (FPGAs) have become very important implementation media for digital circuits. Their programmability has been the key to the success of FPGAs. Embedded Field-Programmable Gate Arrays (eFPGA) are flexible circuits that can be reconfigured by the designer and embedded with devices. The efficient use of these circuits requires complex CAD tools. Placement is One of the steps of the design process for eFPGA. PiCoGA is STMicroelectronics Specific FPGA Chip which is an acronym for Pipelined Configurable Gate Array. The PiCoGA is designed to implement a peculiar pipeline where each stage corresponds to a piece of computation, so that high throughput cir- cuits can be mapped. In this way a sequence of PiCoGA instructions can be processed filling the pipeline in order to exploit parallelism. Along with this configurable unit also preserved its state across instruction execu- tions. A new PiCoGA instruction may directly use the results of previous ones, thus reducing the pressure on the register level. Moreover a tight integration in the pro- cessor core gives the opportunity to use the PiCoGA in many different computational cores. With the arrival of PiCoGA, the problem of multi-computing was solved to achieve a much faster computation. The main goal of this project is to Design a CAD (Computer Aided Design) tool and optimize it which efficiently perform the placement of Reconfigurable Logic Blocks on eFPGA(Embedded FPGA), address the challenges occurring because of the different constraints due to the architecture of chip.