Novel Method to Estimate Static and Dynamic Non-linearity of ADC from a Single Test

Abstract

In spite of great advances in VLSI design and manufacturing, performance of even the best available highspeed/ high-resolution analog-to-digital converter (ADC) is known to deteriorate, while acquiring fast-rising, high frequency and non-repetitive waveforms. ADCs (digitizers) used in HV impulse testing and measurement are constantly required to acquire such waveforms. Errors resulting from a lowered performance can be unacceptably high, especially when higher accuracies have to be achieved, e.g. as in Reference Measuring Systems.Static and dynamic non-linearities are vital indices (estimated independently) for evaluating performance and suitability of ADCs for use in such environments. Typically, estimation of these non-linearities involves 10-12 hours of testing (static test for a 12- bit ADC) or acquisition of millions of samples at high frequencies (dynamic test). So, an efficient estimation of these characteristics is desirable. The novelty of this paper is to propose an efficient method for simultaneous estimation of both static and dynamic non-linearity, from a single test. This is achieved by conceiving a new test signal, which comprises of a high frequency sinusoid (addresses dynamic assessment) modulated by a low frequency ramp (pertains to static part). Details of implementation and results on two digitizers are presented and compared with nonlinearity determined by the existing approach. The time efficiency achievable and good match of result indicates suitability of proposed method.