Implementation of FIR Filter using Soft core Processor on FPGA

Abstract

This paper presents a system level design on reconfigurable architectures say FPGAs or CPLDs. As Altera offer many IP core for their FPGAs, NIOS-II processor is IP core in that family. NIOS-II is equivalent to a microcontroller or “computer on a chip” that includes a CPU and a combination of peripherals and memory on a single chip. SOPC Builder is a powerful system development tool for creating systems based on processors, peripherals, and memories. SOPC Builder enables you to define and generate a complete system-on-a-programmable-chip (SOPC) in much less time than using traditional, manual integration methods. NIOS-II can be programmed suing C/C++ language. It also supports assembly language also. FIR filter is implemented using NIOS-II processor. The output from the same is compared with the result obtained by Matlab. Using Altera’s Mega IP core library, system level design for communication and DSP applications is possible. System level design using NIOS-II processor plays an important role for embedded systems