Analysis of Stereo Imaging Algorithm and Parameterization for Implementation on FPGA

Abstract

In this era of information technology the image processing is applied in various applications such as geo-informatics for e-governance and others. As we know typical satellite images are in very large number and even a single image is of such a high resolution. Hence efficient implementation is required to meet the real time constraints. These image processing algorithms are usually implemented in software but may also be implemented in special purpose hardware to meet timing constrains. Therefore to achieve satisfactory speed up for execution of image processing algorithms special purpose processors like DSPs or DSP-FPGA hybrid architecture can be used.

The aim of this dissertation is to study some compute intensive algorithms of Stereo Image Matching and parameterize it to optimize the implementation on FPGA. The hierarchical image matching algorithm has been studied, implemented and two variations have been proposed: one is to vary the correlation window size that means to use smaller correlation window to reduce the computations involved. The other is to apply new correlation based formula as a cost function of similarity in conjunction with hierarchical image matching algorithm. The results are obtained by applying these two variations and compared with the results obtained keeping correlation window size reasonably large as well as the original normalized cross correlation formula.

These results are analyzed and a novel solution to this problem is proposed which could result in exact matches and good efficiency of the algorithm at the same time without sacrificing required accuracy.