Design and Implementation of Partial Reconfiguration Based Software Defined Radio on FPGA

Abstract

The next generation of communication will be driven by the technology called Cog- nitive Radio that can adapt the environment around it. It adjusts to the changes in the communication medium, modulation schemes, coding method etc. Design of the radio on the recon gurable platform makes it more exible in adapting the demand of communication system. The thesis covers the design of transmitter and receiver on the recon gurable platform like FPGA, so that the modulation scheme can be dynamically adapted depending on the noise in the communication medium. The virtex series of FPGAs are capable of using the high density IP cores for the lter design and communication. The developed system takes advantage of these IP cores to maximize the performance of the Software De ned Radio. Moreover the FPGAs can be con gured partially when in use. This advantage makes it more useful in the SDR applications. Theory of Partial Recon guration of FPGA is also described in the thesis. The Digital Up/Down Converter (DUC/DDC) is the rst and the most important block of any digital radio system. The thesis discusses the design and implementation of DDC and DUC. The output of DUC/DDC can directly be given to the subsequent blocks for modulation/demodulation and coding/decoding purpose. The thesis highlights the design of each block in detail. The thesis discusses the RTL design and implementation of transmitter and receiver on FPGA. The chip used for the design is Virtex 5, xc5vls110t-1 1136. The model driven designs of DDC and all modulator are veri ed using high level simulation and synthesis tools (MATLAB Simulink and Xilinx System Generator). The RTL code for each block is written in VHDL and simulated using Xilinx FPGA software tool. The results have been compared at simulation level. DDC is implemented on Sparten 3E with speed grade of -4 and the real time testing of design is carried out.