Development of Cell Library in nm Technology

Abstract

As mixed - signal circuits becomes larger and more complex , manual creation of the digital parts of these design become more di cult. To simply and speed up the design process, synthesis and place-and-route tools are use to automate much of the design of the digital components. Technology nodes also moving to lower nm technology so several type of nm technology libraries has been developed to be used at di erent stage and part of the design. There is a special emphasis on development of the library that meet the requirement of low power and low leakage using several methodology. To support this requirement my work also moves around development of such standard cell (core) libraries. The detail of certain steps of library development is discussed starts from introduction to library and whole design ow of library men- tioned in brief. The libraries are targeted for nanometer technology and some of these are also to match the requirement of low power. Generation of di erent views is targeted to be used at di erent abstraction level and for di erent EDA tools. At this stage there are still so many scopes to design a libraries which includes cells which minimize the power requirement as well as cooperate to improve the design cycle by reducing the e orts of the designer. To support this CCS views are there for nm technology libraries. CCS characterization ow is also Descibed brie y. Library should be available in well veri ed form. There are several steps to be carried out and at di erent levels on di erent views of library to ensure full veri - cation. Ver cation steps are also disussed in one of the chapter. ASIC design ow is also a kind of veri cation ow for library cells because it shows the performance of library when it actually comes to implementation.I have only covered the front end ow which con rms to timing and fuctionality while backend ow con rms the backend views of the library.