Design & Characterization of Voltage Follower

Abstract

As the CMOS process entering the nanometer scale analog circuit will need to operate in lower and lower supply voltage. This trend is mainly driven by the need of the low power and low voltage requirement in the consumer electronics market. While, scaling down size technology supply voltage do not scale linearly the VT and VDsat is not scaled down linearly either. These facts serious limit the voltage swing in low voltage supply. Many techniques, such as feedback, threshold independent, pseudo di erential, symmetrical Push pull, body driven have been proposed in literatures to reduce the power supply requirement and still retain acceptable performance. In order to meet the critical power and supply voltage requirements of the portable devices, designing some new cells to satisfy the technique developing trend should be primarily considered by present analog circuit designers. The Voltage follower is one of the most important basis cell in analog circuit design. Presently most system require follower to have capability to drive low resistance loads, while at the same time it can handle large output voltage swing and obtained low harmonic distortion. In this report, comparative analysis of di erent voltage followers proposed in the last decade has been done. All analysis have been supported by simulations results. To carry out the simulations Eldo spice, IC Station and Design architect from Mentor Graphics Tools is used. For all about Pre/Post Layout simulation has been realized using 0.5am CMOS process technology and also the layout of Source Follower and Flipped Voltage Follower has been done using 0.5am CMOS process technology.