Implementation of WISHBONE Interface for SOC Integration with Back-end Design Flow

Abstract

As CMOS manufacturing technology scales into deep and ultra-deep sub-micron design, problems with clock skew, clock distribution, on-chip variations, leakage power and on-chip communication in high-speed synchronous designs are becoming increases. This work presents a back-end design flow for high performance ASICs that includes synthesis, ,timing analysis, optimization, floorplan,,powerplan, placement and routing,timing and area optimization,crosstalk, In VLSI design, designers must face many challenges including timing, area, power etc. There is always trade of between area ,power and timing. Larger area means higher manufacturing cost, lower yield. Timing is always most important factor in VLSI Design. Timing will determine the chip performance. Once a circuit has been placed and routed, interconnect delay is known exactly. However,the prediction of interconnect delay even before the (placement and routing) in design is yet important problem. The ability to predict interconnect delay early stages offer advantages. In this thesis there is back-end design flow of WISHBONE interface is introduce using 0.9um(90nm) technology. The WISHBONE System-on-Chip (SOC) Interconnection is a method for connecting IP cores together to form integrated circuits. The gate count for WISHBONE block are 124623 and Max Operating Condition is 1.32V and 125 degree centigrade and Min Operating condition is 1.08 V and -40 degree centigrade and clock frequency is 200MHz. In recent years, the chip leakage power may be larger than the chip dynamic power because the semiconductor process technology progresses quickly .Therefore, leakage power reduction becomes an important issue for low power circuit designers.Leakage is increasing exponentially as CMOS technology scaling down. At Synthesis stage and Clock Tree Synthesis stage proposed flow is using multivt(Multiple Threshold voltage) library(Swapping of cells) which uses HVt(High threshold voltage),LVt(Low Threshold Voltage) and RVt(Regular Threshold voltage) cells.