Methodology/Flow Enhancement to increase Verification Efficiency in Multi-core Microprocessor

Abstract

Design verification is one of the most challenging tasks in hardware development. With the ever increasing complexity of digital systems, veri cation e ort has become the primary bottleneck in circuit design, consuming up to 70% of the total e ort.On one hand, Moore's Law reminds us "that the number of transistors on an integrated circuit for minimum component cost doubles every 24 months". With this increased number of transistors, design size grows as more functionality is being integrated on to a single chip. A more critical problem faced by ASIC designers concerns the verification of these complex digital systems. Design verification is the process of ensuring correctness of the design throughout the design stages. Verification complexity is growing proportionately with the square of the increase in design complexity. Severe competition in the industry is squeezing us on both cost of the products and time-to-market requirements. In response we are forced to "optimize" design schedules and team headcounts. On the design side, teams have addressed the challenge by adopting e cient design techniques that mandate code reusability, using well defined interfaces and best coding practices. Meanwhile, veri cation typically takes 60-75% of the CPU/Graphics development effort; so the veri cation teams must also increase their efficiency. The thesis describes the faster design debug capabilities in veri cation domain based on the extracting smaller design module from whole big design and verify it iteratively rather than verify whole design again and again after making changes and as a result verification efficiency is increased. This also includes the regression analysis and making such analysis simpler using a bucketing mechanism of test failures having same failing reason and debug them very quickly which also leads to reduce verification time.