Design & Implementation of Mitigation Techniques for Single Event Upset in SRAM FPGA

Abstract

The FPGAs (SRAM BASED), operating in space environment, are perturbed by charged particles, which a ect the circuit in different ways. This work details the mitigation techniques for one of these effects called Single Event Upset(SEUs). With the progress of technology, the highly scaled devices exhibit an increased sensitivity to SEUs due to a reduced feature size and a proportional increase in device density. FPGA based designs are more susceptible to SEUs compared to ASIC designs and it is more harmful when FPGAs are used in space and defence applications. The Goal of the project is to Design, Develop and Implement the mitigation techniques for SEU, which can be carried out using various techniques.This thesis addresses some developed solutions to turn CMOS memory cells SEU immune by system where software solutions and hardware redundancy is used to mit- igate SEU. Various design based solutions like Spatial Redundancy(Triple Modular Redundancy), Temporal Redundancy and Scrubbing(Recon guration) are discussed in the thesis. Apart from the mitigation, infrequent and unpredictable nature of real SEUs, small scale testing of their e ects and system veri cation is impractical. To perform this tasks the SEU monitor system is designed and implemented on FPGA. The system along with controller macro can emulate an SEU by deliberately injecting an error into the FPGA con guration so that its subsequent detection and correction can be con rmed. It can also be used to assess SEU mitigation circuits implemented in a design. Finally, the Self Correcting System is implemented using the SEU monitor system and self recon gurable system, which detects and corrects the error. If the correction of error is not possible then it recon gure the user design. The thesis describes the operation and architecture of the proposed logic design as well as its implementation in Xilinx virtex-5 FPGA.