Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/2392
Title: Design, Simulation and Hardware Implementation of Facts Controllers for Reactive Power Compensation of Transmission Lines
Authors: Baing, Avdhut D.
Keywords: Electrical 2009
Project Report 2009
Electrical Project Report
Project Report
EE (PEMD)
Power Electronics, Machines  & Drives
09MEE
09MEE002
PEMD
PEMD 2009
Issue Date: 1-Jun-2011
Publisher: Institute of Technology
Series/Report no.: 09MEE002
Abstract: For a secure power system operation, voltage stability is of great concern. In an ideal power system, the voltage at receiving end should be same as that of the sending end and also the voltage should be of good quality, i.e. no uctuations in voltage even at changing loads. In this project report, voltage drop is compensated in two di erent ways. Using shunt and series compensation. The compensation is done using FACTS technology, viz. Thyristor Controlled Series Capacitor (TCSC) and Thyristor Switched Capacitor (TSC) for series and shunt compensation respectively. Both the FACTS controllers provide dynamic control over the compensation. TCSC provides a wide range of compensation by changing the ring angle and also limits the fault current in case of faults. TCSC provides protection against faults by setting the operation mode into the inductive mode. Also TCSC helps increasing the power transfer and maintain the power system stability by improving the load angle. TSC provides control against dynamic heavy load changes to maintain voltage drop minimum and retain the power quality. Closed loop model of TSC shows the maintaining of voltage even for load changes. Simulation of all the models are done in MATLAB7.8. The models are kept well in synchronism with frequency changes of the power system hence better performance is obtained. Hardware model of TSC is also developed in the laboratory for scale down values of load and the compensation results are obtained. The actual results are compared with simulation results to check the satisfactory performance of the hardware model.
URI: http://hdl.handle.net/123456789/2392
Appears in Collections:Dissertation, EE (PEMD)

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