Analysis and Design of Analog to Digital Converter for Ultra Wide Band Application

Abstract

Ultra-Wideband (UWB) communication is a recent high speed wireless technology that uses sub-nano second pulses to transmit information. According to United States Federal Communications Commission (FCC), a UWB technology is a form of wireless communication in which signals occupy a wide bandwidth, greater than the lesser of 500MHz or 20% of the center frequency of the signal is consider as an ultra wide band signal. A high speed low/medium resolution Analog-to-Digital converter (ADC) is required for processing the above signal. However, designing ADC with high sampling rates ( 500Msamples/sec) is still a challenging task even at low resolution. A comparator is one of the important and essential blocks for realizing an ADC. A simple two stage comparator has high propagation delay and power consumption. So, a clocked latch comparator with pre-ampli er has been analyzed and designed. Di erent architectures for realizing ADC at very high sampling rates to minimize the power consumption have been investigated. Flash ADC is obvious design choice for high sampling rates. Therefore, a 5-bit Flash ADC with 500Msamples/s sampling rates has been analyzed and designed. However, the exponential increase in the comparator count with resolution results in more power consumption. Therefore, to reduce the power consumption while retaining the resolution an Asynchronous binary search ADC for Ultra wide band application has been analyzed and designed. The simulations of all the designs are done in cadence UMC 0.18um technology with a 1.8V power supply. The clocked latch based comparator consumes 0.442mw power at clock speed of 500MHz. Flash ADC consumes 13.64mw of power with 1.8V supply voltage at clock speed of 500MHz with propagation delay of 1.135ns. A 5-bit Asynchronous binary search ADC has been designed, it works for sampling rates upto 300Msamples/s and consumes 4.113mw of power from 1.8V supply voltage. As compared to ash ADC which consumes 9.5346mw at 300Msamples/s, the power consumption in Asyn- chronous ADC is halved. In this thesis, an ADC architecture with reduce power consumption has been designed.