Sense Amplifier Based D Flip Flop Implementation in 0.18μm Technology

Abstract

The traditional flip flops and latches suffer from the large delays and the race conditions. The paper describes a new approach to the D flip flop design using the sense amplifier. The previous efforts in the same direction were made at the 0.25μm technology exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops. The paper discusses the flip flop at 0.18μm technology. The output latch of proposed circuit can be considered as a hybrid solution between the standard NAND based SR latch and the N-C2MOS approach. The present technology exhibits improvements in clock-to-output delay and power dissipation with respect to recently proposed high-speed flip-flops.