Single Event Upset Mitigation Techniques Implementation Based on TMR

Abstract

FPGAs have become an appealing solution for space-based remote sensing applications. But, FPGA-based designs are more susceptible to single-event upsets (SEUs) compared to ASIC designs. Soft error rate (SER) estimation is a crucial step in the design of soft error tolerant schemes to balance reliability, performance, and cost of the system. Previous techniques on FPGA SER estimation are based on time-consuming fault injection and simulation methods. The scrubbing methods of the TMR is also discussed where the traditional TMR is not sufficient to correct the SEUs. This paper also presents a unique SEU (single Event Upset) mitigation technique based upon Temporal Data Sampling for synchronous circuits and configuration bit storage for programmable devices. The design technique addresses conventional static SEUs induced errors that can result in data loss for reconfigurable architectures. A unique hardening technique is described which addresses SEE (Single Event Effect) problems which result in data loss in deep submicron microcircuits in space radiation environments. This hardening technique, addresses both conventional static SEUs (Single Event Upsets) and SET (Single Event Transient) induced errors.