Development of Controllability Observability Aided Combinational ATPG with Fault Reduction

Please use this identifier to cite or link to this item: http://10.1.7.192:80/jspui/handle/123456789/2817

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DC Field	Value	Language
dc.contributor.author	Dhare, Vaishali	-
dc.contributor.author	Mehta, Usha	-
dc.date.accessioned	2012-02-02T05:45:42Z	-
dc.date.available	2012-02-02T05:45:42Z	-
dc.date.issued	2010-07-23	-
dc.identifier.citation	First International Workshop on VLSI Design 2010 , Chennai, July 23-25, 2010, Page No. 682-692	en_US
dc.identifier.uri	http://10.1.7.181:1900/jspui/123456789/2817	-
dc.description.abstract	With the Increase improvement in VLSI Design and Progressive Complication of Circuits, an efficient Technique for test pattern generation is necessary with the intention of reducing number of faults and with the use of testability measures.	en_US
dc.relation.ispartofseries	ITFEC022-5	en_US
dc.subject	ATPG	en_US
dc.subject	Fault Equivalence	en_US
dc.subject	Controllability	en_US
dc.subject	Observability	en_US
dc.subject	EC Faculty Paper	en_US
dc.subject	Faculty Paper	en_US
dc.subject	ITFEC022	en_US
dc.subject	ITFEC010	en_US
dc.title	Development of Controllability Observability Aided Combinational ATPG with Fault Reduction	en_US
dc.type	Faculty Papers	en_US
Appears in Collections:	Faculty Papers, EC

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