Novel Topologies of CMOS Second Generation Current Conveyor for Low Voltage Low Power Applications

Abstract

From the beginning of era of integrated circuits, the voltage mode operational amplifier has served as the basic building block in analog circuit design. Since then, new integrated analog circuit applications have emerged and the performance requirements for analog circuits have changed. The voltage-mode operational amplifier circuits have limited bandwidth at high closed-loop gains due to the constant gain-bandwidth product. Furthermore, the limited slew-rate of the operational amplifier affects the large-signal, high-frequency operation. To overcome the above limitations of voltage mode architectures, current mode circuits have begun to emerge as an important class of circuits with properties that enable them to rival their voltage mode counterparts in a wide range of applications. A well-known current-mode circuit is the Current-Feedback Amplifier (CFA) [10,11,12,13,14]. The CFA can be implemented using second generation Current conveyor (CCII).In 1968 Smith and Sedra introduced the first generation current conveyor (CCI) [1] and in 1970 the second generation current conveyor (CCII) was proposed by the same two authors [2]. Since then CCII, which is essentially a combined voltage and current buffer, has proved to be functionally flexible and versatile, rapidly gaining acceptance as both a theoretical and practical building block [3,4]. Firstly, CCII was realized in bipolar technologies and, recently high-performance CCII circuits have been designed in CMOS process [6-25]. In this thesis, basic current Feedback amplifier (CFA) architectures are reviewed and verified. The CFA can be successfully implemented CCII followed by Voltage buffer. The existing CCII topologies are reviewed and discussed. The thesis focuses on the three novel architecture of CCII. The first (CCII) is based on wide swing cascode current mirror which reduces the distortion and gain error to a great extent.The second design is derived from simple current mirror based CCII [24-25] in which the input nMOS level shifter is replaced by OTA level shifter and output voltage follower is replaced by Flipped voltage follower. The third CCII is implemented to overcome the bias current dependency on output offset found in the second proposed CCII. These designs are low voltage, low power, wideband and very compact. Moreover a novel block has been introduced, which is named as differential input CCII (DICCII).Two new DICCII are proposed. These architectures are modeled using small signal analysis and they are simulated using eldo-Spice. The designs are also compared with the state of art designs. All proposed CCII architectures are simulated using systematic and random process variations of 5% on external and process parameters. The external parameters like supply voltage and temperature and process parameters like mobility and threshold voltage are varied about 5% on top of all design corners. The post layout simulation is also carried out and compared with pre-layout simulation for all proposed architectures. The simulation results shows that all of above proposed architectures perform satisfactory under parametric variations.