Low Power Folding and Interpolating Analog to Digital Converter : Optimization of Area and Power For Medium Resolution Applications

Abstract

The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs). The Folding and Interpolating technique has been introduced to CMOS Analog to Digital Converter in the 1980’s. Folding and Interpolating ADCs have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The architecture also offers advantages such as less die area, low power consumption, and less complexity. In Folding and Interpolating ADC, data conversion is carried out in two parallel blocks- Coarse Converter (MSBs) and Fine Converter (LSBs). In this thesis, fundamental of analog to digital conversion and various ADC types are reviewed and discussed. The details of various sub blocks of Folding and Interpolating ADC and existing solutions are described in the thesis. The thesis focuses on design of low power Folding and Interpolating ADC for medium resolution applications. The architecture improvements and optimization of various sub blocks are performed in the thesis. The pre processing block-folding amplifier is designed to reduce power consumption and settling time. The designed folding amplifier reduces power consumption by folding factor times compared to conventional folding amplifier. The architecture uses novel cascaded folding amplifier to achieve high folding factor. In ADC, comparators consume the major part of the total power. The converter architecture is designed with reduced number of comparators and minimum hardware. For further reduction of latency and number of comparators, folding amplifier is used in the design of coarse and fine converter both. To reduce the power consumption, encoder based on XOR-OR logic is used. Due to cyclic output of folding block comparison, number of comparators required is only 10 in case of 6-bit converter. Design criteria for all the blocks and optimization of area and power for medium resolution applications are discussed in the thesis. Systematic and random variations in process parameters, supply voltage and temperature are posing a major challenge to the future high performance VLSI design. Using Monte Carlo (MC) simulation, the effect of process variation is studied. Also systematic and random variations in voltage and temperature are observed using simulation results. The post layout results of various sub blocks are also obtained. The design is simulated using 0.35mm technology at 3.3V. At 200MHz, Signal to Noise Ratio (SNR) obtained is 37.9 dB and Spurious Free Dynamic Range (SFDR) is 58dB. For the implemented design, Effective Number Of Bits (ENOB) is 6.003, total power required is 11.7mW and Differential Non-Linearity (DNL) is less than 0.65.