Characterization & Comparative Analysis of High Speed CMOS Comparator for Pipelined ADC

Abstract

In today’s high speed low power era, there is an increasing demand of a High Speed Comparator for ADC, DAC and various other applications in an analog and digital domain. This paper describes and analyzes five different architecture for low power and high speed comparators. In this paper, authors have analyzed and simulated the designs using TSMC 0.35 μm CMOS technology with ±2.0V for preamplifier based comparator and ±1.8V power supply for dynamic comparators. The simulation results allow the circuit designer to fully explore the tradeoffs in comparator design, such as offset voltage, speed, power and area for Pipelined A/D Converters. Prelayout and postlayout simulations are carried out using Eldo SPICE tool and layout using IC Station.