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DC Field | Value | Language |
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dc.contributor.author | Khan, Umar Faruque | - |
dc.contributor.author | Naik, Amisha | - |
dc.contributor.author | Bose, S. C. | - |
dc.date.accessioned | 2012-05-25T07:41:08Z | - |
dc.date.available | 2012-05-25T07:41:08Z | - |
dc.date.issued | 2009-11-25 | - |
dc.identifier.citation | National Conference on Current Trends in Technology, NUCONE-2009, Institute of Technology, Nirma University, Ahmedabad, November 25-27, 2009, Page No. 39-46 | en_US |
dc.identifier.uri | http://10.1.7.181:1900/jspui/123456789/3309 | - |
dc.description.abstract | To describe paper, we have coined one terminology called Scaling Factor (S). Scaling Factor means varying both channel length (L) and channel width (W) such that its aspect ratio (W/L) remains same. Here we are varying scaling factor from 1 to 10 and analyzing its effect on all parameters of a two stage CMOS op-amp through graphs and then combining all graphs in a single graph. And then generating the equation for all graphs using curve fitting equations and summarizing it into one general formula that is applicable to all parameters of a two stage CMOS op-amp and also plotting all graphs again which is doing comparison between simulated graph and graph through curve fitting equation. Finally, three layouts of a two stage CMOS op-amp at scaling factor S =1, 5 and 10. And then plot one more graph between layout area and scaling factor and then add this graph to a combined graph is plotted. The comparison between pre-layout and post-layout simulation curve of all parameters of two stage CMOS op-amp with respect to scaling factor (S) is done. The design is implemented in the range of 0.35μm to 3.5 μm with a 3.3V as power supply. | en_US |
dc.publisher | Institute of Technology, Nirma University, Ahmedabad | en_US |
dc.relation.ispartofseries | ITFEC007-5 | en_US |
dc.subject | Scaling Factor | en_US |
dc.subject | EC Faculty Paper | en_US |
dc.subject | Faculty Paper | en_US |
dc.subject | ITFEC007 | en_US |
dc.subject | NUCONE | en_US |
dc.subject | NUCONE-2009 | en_US |
dc.title | Effect of Channel Length (L) Reduction on the Parameters of Two Stage CMOS Op-Amp while Keeping the Same Aspect Ratio | en_US |
dc.type | Faculty Papers | en_US |
Appears in Collections: | Faculty Papers, EC |
Files in This Item:
File | Description | Size | Format | |
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ITFEC007-5.pdf | ITFEC007-5 | 1.3 MB | Adobe PDF | ![]() View/Open |
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