Recon gurable Architecture of Digital Modulator and Demodulator for SDR on FPGA

Abstract

The next generation of communication will be driven by the technology called Cognitive Radio that can adapt the environment around it. It adjusts to the changes in the communication medium, modulation schemes, coding method etc. Design of the radio on the recon gurable platform makes it more exible in adapting the demand of communication system. The thesis covers the design of Direct Digital Synthesizer ,Digital Modulator and Demodulator on recon gurable platform like FPGA.so that the modulation scheme can be dynamically adapted depending on the noise in the communication medium.The Design of DDS is done on spartan 3 with speed grade of -4 while Digital Modulators and Demodulators are design on Virtex 5. The Virtex series of FPGAs are capable of using the high density IP cores for the Filter design and communi- cation. The developed system takes advantage of these IP cores to maximize the performance of the Software De ned Radio. Moreover the FPGAs can be con gured partially when in use. This advantage makes it more useful in the SDR applications. Here design of di erent Modulator and Demodulator is done using Simulink Model with help of System Generator Block Set and Xilinx Block Set and the same as been veri ed using Hardware in Loop Veri cation .The chip used for the design is Virtex 5, xc5vls110t-1 1136.