Implementation of "Early Design Checks" for Communication & Memory Interface IPs

Abstract

As the complexity of the SOC increases now a days, the inaccuracies during RTL design also increases which may tend to a bug during later stages of design. To avoid such conditions and to have completeness and done-ness during RTL designing, Early Design Checks are used. Early Design Analysis can nd most comprehensive design problems related to Clocks, Resets, Clock Domain Corssing(CDC) and Design for Testability(DFT) which could not found out in the veri cation of the design but this may capture at the netlist level which will cause a design respin and TTM will increase. Early Design Checks nd these issues at RTL level, so reduce design respin time. To generate the netlist from the RTL, Designer needs synthesis constraints. These Constraints need to be accurate for the quality netlist. Early Design Analysis also helps to generate synthesis constraints automatically with the help of tool. This automation reduces the human e orts to generate more accurate constraints. For Early Design Checks, a tool named Spyglass(From Atrenta) is used to carry out this analysis on di erent IPs. Spyglass will observe problems related to di erent IPs and ensure that the applied solution is feasible at every stages of Early Design Analysis. Spyglass provides a way to achieve early closure and predictability of a RTL block right at the source. With the help of it, down stream issues can be predicted earlier. So, the RTL modi cation is possible early at the Design cycle.