Developing Kits for Mask Programmable IPs

Abstract

In semiconductor design standard cell methodology is a method of designing Applica- tion Speci c Integrated Circuits (ASICs) with mostly digital logic features. Standard cell methodology is an example of design abstraction, whereby a low level Very Large Scale Integration (VLSI) layout is encapsulated into an abstract logic representation such as a NAND gate. In physical design of an ASIC among the various process involved, the Placement and Routing of cells is one of the important steps. Various Place and Route tools are used for this purpose. This project mainly deals with running the place and route ow on such tools or Kits. Soc Encounter kit, Sierra kit and IC Compiler are the place and route kits available for placement and routing. In this project the automation of the place and route ow has been done for these kits. This report explains the basic place and route task ow which is common to all the kits. It also explains the basic Engineering change order ow done on ECO kit. This report includes the benchmarking of the con gured libraries i.e. the analysis of the libraries obtained by inserting special fortune ller cells during place and route based on various parameters.