Implementation of USB Flashing Utility for Embedded MPU SPEAr

Abstract

Embedded system with OS requires the boot-loader to boot the operating system (OS). Depending on the System, it can be booted in the various booting mode from either memory or a communication interface. Booting from network or serial interface can be used to upgrade the ash memory on the board. USB ashing utility is the PC based application used to upgrade the ashes in the SPEAr based Embedded SOC. USB Flashing Utility architecture uses di erent components at di erent stages to accomplish ashing operation. USB ashing utility is the tcl script which is compatible to the Windows and Linux environment. It uses the libusb for connection and the Kermit protocol for transfer of le. In the very rst stage the USB boot mode support available in SPEAr platform BootROM is used. In this mode the BootROM enumerate itself as a generic USB device capable of receiving and executing any binary transferred by USB host. As soon as a binary/ rmware is transferred from USB host, BootROM executes it and then the control can be taken over by the rmware itself to present any desired interface or to perform any task. In the USB ashing utility this rmware is a DDR driver and customized u-boot to enumerate SPEAr device as a serial device (over USB) which can then be used at Host to send any u-boot command. These commands are being used by ashing utility to perform ashing operation. The Host side ashing GUI and command interface hides this complexity by o ering a simple interface for ashing operations. With the advent of the System-on-Chip technology, designs are becoming highly complex. IP based design for System on chip are encouraged as it shorten the design cycle time , reduces design cost and allows the IP design reuse. The IP based design must be veri ed in the Pre-silicon Veri cation Environment at Block Level and SoC Level. GPIO IP is widely used in the RTL design of System on Chip. It provides the interface for the General Purpose Input Output. It can also be used to generate the edge and level triggered interrupt.