Characterization, Design & Simulation of Low Power High Speed CMOS Comparator in Deep Sub-micron Technology

Abstract

One of the factors driving the downscaling of CMOS technology is the ever present drive for price-per- performance of electronics circuits. The minimum dimensions get smaller and maximum supply voltages are reduced due to reliability issues. The re- duction in supply voltage is not necessarily followed by an equal reduction in threshold voltage, which limits the available voltage headroom.These nano-scale CMOS tech- nologies o er many challenges. The challenges have, in some cases, brought success to simpler topologies that have shown some of the advantages of nano-scale CMOS for analog circuits. One advantage of scaling down is the increased speed.However, as we move towards smaller feature size processes, the process variations and other non-idealities will greatly a ect the overall performance of the device. One such application where low power dissipation, low noise ,high speed ,less hysteresis ,less O set voltage are required is Analog to Digital converters for mobile and portable devices. The performance limiting blocks in such ADCs are typically inter-stage gain ampli ers and comparators. The accuracy of such comparators, which is de ned by its o set, along with power consumption, speed is of keen interest in achieving over- all higher performance of ADCs. In the past, pre-ampli er based comparators have been used for ADC architectures such as ash and pipeline. The main drawback of pre-ampli er based comparators is the more o set voltage and static power dissipa- tion. To overcome this problem, dynamic comparators are often used that make a comparison once every clock period and require much less o set voltage and power dissipation. In the literature, various kinds of CMOS comparators can be found.Among the circuits proposed in literature, some are concerned with speed , some may be emphasizing on low power and high resolution, some on o set cancelation.In this thesis, various kinds comparators will be fully analyzed in terms of their advantages and disadvan- tages along with operating principles and experimental results of the speed, power consumption, and o set voltage at a limited area.In this way a modif ed dif ferential paired comparator having speed of 36Ghz with a power consumption of 18uw can be obtained. The modi ed di erential comparator presented here is based on the idea to ensure that all of the input transistors are always working in the saturation region at the re- generation time while other transistors that consume the voltage margin are removed. To achieve these objectives, the modi ed di erential comparator removes two current sources from the tail of the di erential pair, and replaces them with a CMOS switch (or NMOS switch) controlled by a clock.Two PMOS switches are also inserted so that the input transistors remain in saturation for more time to get full swing at the output.The comparators are designed in TSMC 0.35 m, 0.13 m 0.09 m Technology with +/-2.5V, +/-1.5V and +/-1V power supply. Comparative analysis is done for the di erent topologies.E ect of scaling and power supply variation are also observed in the analysis. The Pre layout Simulations are done using Eldo Spice Tool and layout is made using Mentor Graphics Backend Design Tools like IC Station and DA-IC(Design Architect)