A Novel Approach To Power Optimization In High Frequency Microprocessor Design Using An Intelligent Slack Manipulation Algorithm

Abstract

Versatile form factor and battery backup is one of the major focus in electronics industry. This leads to exploration more power reduction opportunities in all products . Tradeoffs in area , power and delay are the order of the day in VLSI field. However in some cases we can actually exploit some resources and manipulate them in such a way to optimize other resources rather than mere tradeoff. One such way is to squeeze extra margin from positive slack paths to gain power reduction. This Thesis is an outcome of efforts directed to develop and test an algorithm which can utilize the extra slack margin available for the cell by intentionally engineering delays in the cells in the design and hence leading to a more power efficient design. This Algorithm also physically implements addition of delays to cells by downsizing the cells and then swapping suitable cells in the design by the corresponding lower leakage cell instances from the available design library. This is done in manner such that the original timing on lower slack margin paths are not affected and the critical path slack remains essentially the same. This Thesis also discusses various aspects related to Static Timing Analysis , Slack calculation and Slack Budgeting and Power Dissipation which were the prerequisites in development of this algorithm This Thesis also discusses various aspects related to Static Timing Analysis , Slack calculation and Slack Budgeting and Power Dissipation which were the prerequisites in development of this algorithm.