Evaluation and Porting of High Speed Dual Port SRAM Compiler in Submicron Technology

Abstract

This thesis explores the performance characterization of a Static Random Access Memory (SRAM), the design validation of the SRAM. Design Validations include Marginality Analysis, Power Estimation, Pin Cap Measurement, Leakage Measure- ment. Main focus on optimizing area, delay and power at circuit as well as on architectural level. SRAM Compiler has main two types of con gurations Single port and Dual port. This thesis is more focus on Dual port SRAM because of their complexity is higher than single port SRAM. Dual port SRAM has eight transistors structure. SRAM design has to cope with a stringent constraint on the area and speed to achieve high integration density at high speed in modern system-on-chips (SoCs). As dimensions scale down to nanometer regime, the variations in CMOS transistor parameters, e.g., the threshold voltage , width, length, increase steadily due to random dopant density uctuations in channel, source and drain. Therefore, two closely placed, supposedly identical transistors, have important di erences in their electrical pa- rameters, leakage, delay and as and make the design of the SRAM less predictable and controllable. Moreover, small threshold leads to high leakage. This thesis fo- cused on the analysis of the Dual-Port SRAM Compiler. Di erent parameters of SRAM i.e. Performance (current ), Timing, leakage analysis of Dual port SRAM all are analyzed. All these parameters are measured with PVT variations. Monte Carlo Simulation is used to model the Process variations. To reduce the power dissipation due to discharge of bitlines from Vdd to 0v during the time when word line selected we made use of self-time concept. This can be done either by dummy structure approach. The dummy structure approach is more immune to process parameter variation because the dummy I/O is similar to normal I/O, therefore inter-chip variation is negligible. This SRAM has dummy column discharges through the dummy cells. This discharge is faster then normal discharge so the reset signal sense ampli er enable signal can be activated before the normal discharge exceed voltage di erence between bitlines being resolve by sense ampli er. The basic application of Dual-port SRAM is in Video SRAM, which allows the memory to allocate one channel to refreshing the screen while the other is focused on changing the images on the screen. Since video memory chips are used in much lower quantities than main memory chips, they tend to be more expensive.