Evaluation of SRAM Compiler in Shrink Technology

Abstract

Of all the changes that the shrinking technologies have brought about, an important one is the impact of parasitic resistance on circuit delays. Till 65nm the Memory IP developers were signing-o timing using only parasitic capacitance and resistors were considered only in the power nets for IR drop analysis. But with newer technologies the impact of the parasitic resistance on the signal delays of the circuit is substantial and cannot be ignored. To provide sign-o quality timing numbers to customers, apart from delays due to signal net RC, it is also important to quantify the impact of IR drop on the signal delays. For example, in older technologies the impact on resistive drop of signal-net routing delay was negligible (less than 2%) but in shrink technologies this number is rapidly increasing (more than 10%). In this paper, we will be discussing about our ow to qualify memories with accurate simulation and reasonable runtimes. Fast Spice simulator development has long been driven primarily to cater to the need of simulating the given circuit as quickly as possible, even at the cost of not addressing perennial issues faced in complex blocks such as memories. Modern memories are loaded with features complicating the characterization process while maintaining high level accuracy required. The paper has highlighted a few speci c cases in various modes of characterization and design validation, where improved simulator performance could enable design extract an additional pound of esh in term of performance. Solutions to some of these issues have been discussed in the paper which XA fast-spice simulator provides, while others have been included to explain the issue and requirements to solve the issue.