Design and Development of Standard cell and eCL library

Abstract

As circuit becomes larger and more complex and the technology moves to lower nodes, manual creation of the digital modules of these design become more di cult. To simplify and speed up the design process, synthesis and place-and-route tools are used to automate much of the design of the digital domain. To support this requirement my work also moves around development of such standard cell libraries. The internship mainly involved making layouts of Standard cell and eCL libraries from given schematics and packaging them. Occasionally charac- terizing them using ELDO Simulator to measure input capacitance, prop- agation delay, rise time etc. and running Place and Route ows on them. The details of all steps of library development are discussed which starts from introduction to library and whole design ow. Generation of di erent views is targeted to be used at di erent abstraction level and for di erent EDA tools. In the ow, rstly the schematics are made. Then layouts are made from the schematics. We run DRC, LVS on these layouts. Them we apply DFM on the layouts. Then there is functional veri cation of the extracted netlist from the layout. Further these cells are characterized for timing and power. Finally a place and route is performed using these cells. Also a Testchip is made for each library which is used for silicon validation of the same.