Development of System Level Memory Model for Prabilistics Error Introduction for Reliable Aware Intelligent Memory Management in an SoC

Abstract

As the geometries of the transistor reach the physical limits of operation, one of the main design challenges of System On Chips (SoCs) will be to provide the sup- port against permanent and intermittent faults that can occur in the system. One of the most critical elements that a ect the correct behavior of the system is the unreliable operation of on chip memories. In this dissertation report, we present a solution for the reliability of on chip memories of SoCs for sub nm technologies. This report is concentrating on the Reliability with respect to the Process, Voltage and Temperature variation. In sub nm technology this PVT variation e ects are more visible. These variations is random in nature, the main challenge is to monitoring these random variation and taking some action to increasing SoC reliability. We introduce the concept of RAIMM (Reliability Aware Intelligent Memory Manage- ment) it allows to examine the e ects of Process, Temperature and voltage (PVT) variation on system memories. It also allows to continuously reliability prediction for system memories and system level solutions for unreliable memories.