High Performance and Low Power VLSI Design for SoC Applications

Abstract

VLSI design is based on the PPA (power, performance and area) of the fabricated devices. Modern day VLSI devices require high performance at low power in a lesser area. This is achieved by device scaling in current technology. High performance, portability and reliability have played a major role in the emergence of low-power, low-voltage, and high speed digital circuit designs. The need for uninterrupted operation of the portable devices (extend the battery life) designed for high speed network computing, to have inexpensive packaging and cooling systems, and to reduce the weight and size of the equipment were the driving forces in this regard. Reducing the power dissipation while keeping the performance una ected or to achieve even higher performance is indispensable for state of the art VLSI de- signs. This work contains introduction to novel technology and several methods to achieve high performance, low power VLSI designs. The wide range of techniques discussed here is used in modern VLSI systems to achieve the above-mentioned goal. Limitations of conventional technologies in meeting with the VLSI design cri- teria in the nano-metric design regime are discussed. A new class of VLSI devices fabricated based on Silicon-On-Insulator technology, namely Fully-Depleted Silicon- On-Insulator (FDSOI) is discussed. Generic information about high speed and low power enablers of ASIC/SoC designs is provided.