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DC Field | Value | Language |
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dc.contributor.author | Patel, Ashish | - |
dc.date.accessioned | 2012-06-26T08:32:48Z | - |
dc.date.available | 2012-06-26T08:32:48Z | - |
dc.date.issued | 2012-06-01 | - |
dc.identifier.uri | http://10.1.7.181:1900/jspui/123456789/3485 | - |
dc.description.abstract | In semiconductor industry, technology changes very fast. So now a day TTM (Time To Market) becomes very short. So it has become very necessary to estimate the die size before implementation of any chip. This project deals with a GUI which shows the IO cells require according to parameters (i.e. voltage, frame, frequency etc.) to build IO Ring. This GUI provides IO Portfolio and Ring solution in 45nm technology. You can use this tool for any technology to estimate the die size of any IO Ring. | en_US |
dc.publisher | Institute of Technology | en_US |
dc.relation.ispartofseries | 10MECV25 | en_US |
dc.subject | EC 2010 | en_US |
dc.subject | Project Report 2010 | en_US |
dc.subject | EC Project Report | en_US |
dc.subject | Project Report | en_US |
dc.subject | 10MEC | en_US |
dc.subject | 10MECV | en_US |
dc.subject | 10MECV25 | en_US |
dc.subject | VLSI | en_US |
dc.subject | VLSI 2010 | en_US |
dc.subject | EC (VLSI) | en_US |
dc.title | GUI based Die Size Estimation Tool with IO Portfolio Selection System | en_US |
dc.type | Dissertation | en_US |
Appears in Collections: | Dissertation, EC (VLSI) |
Files in This Item:
File | Description | Size | Format | |
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10MECV25.pdf | 10MECV25 | 1.23 MB | Adobe PDF | ![]() View/Open |
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