Characterization,Design & simulation of Digital to Analog Converter in Deep-Submicron Technology

Abstract

The DAC requirements on today's telecommunications equipment are very hard. Most of the signal processing is done in the Digital domain, but the information has to be transferred with Analog signals, and therefore Analog-to-Digital convert- ers (ADC) and Digital-to-Analog converters(DAC) are crucial building blocks. In this report we concentrate on the matching properties of R-2R and Segmented DAC. Because transistor level simulations are time demanding, we need to approach the problems on a higher level of abstraction. A mathematical model of so called linearly graded mismatch has been developed and analyzed for a particular DAC structure. A DAC structure that will reduce the in uence of linearly graded mismatch has been developed, and two sets of DAC chips with di erent types of current switches have been implemented. Some design issues for mixed mode applications in general, and especially DAC, are also discussed. In this report, comparative analysis of R-2R and segmented DAC (3 bit and 4 bit) proposed with most of the speci cation in the last decade has been done. All analysis have been supported by simulations results. To carry out the simulations Eldo spice, IC Station and Design architect from Mentor Graphics Tools is used. For all about Pre Layout simulation has been realized using ( 0.35um & 90nm ) CMOS process technology and the Post layout of R-2R and segmented DAC has been done using 0.35 m CMOS process technology.