Verification of D3G Module for Wireless Chip in 65nm

Abstract

Today, in the era of multi-million gate ASICs, reusable Intellectual Property (IP), and System On Chip (SOC) designs, verification consumes about 70% of the design effort. The number of verification engineers is usually twice the number of design engineers. When design projects are completed, the code that implements the test benches makes up to 80% of the total code volume. Verification of design is done at various levels of design phase The project scope for verifying the D3G module. This module implements DigRF3G interfaces on Baseband IC. It is used to transfer data and control information between RFIC and BBIC. Verification of module is done using VERA®. The prerequisite of the undertaken project is to thoroughly understand the module under study and VERA the verification tool. In the first phase of the project task assigned was to deal with learning the verification tool, debugging various test cases. It demanded technical in-depth of each test case, followed by locating-defining the problem, find the cause and report it. The second phase of the project task involved random verification for functional coverage of the module that stresses demands for the conceptual understanding of the process of random verification. The next part pf the project involved Common Power Format activity for the same module, inorder to transfer the IP from 65nm to 45nm. In the fourth phase of the project task assigned was to perform the code coverage activity for the same module. This volume describes various stages of the training cum project work. Apart from the above, it discusses about the VERA implementation and issues, the common power format and code coverage. Of course, only a few of the codes and algorithms are presented maintaining the confidentiality of the organization.