Development of DFT for TMC IP in SoC

Abstract

Project deals with the DFT Implementation for the Design, test terminology and scan design techniques. It also involves the verification of JTAG tests and patterns for design at RTL level and Gate level using TetraMax ATPG tool.Verification of TMC IP as writable register done through main TAP controller of JTAG. All DFT structures are driven/checked by using JTAG UDRs and JTAG IRs. All JTAG UDRs and JTAG IRs are driven/checked by using JTAG VIP through JTAG IF except for the ATPG and Boundary Scan, all DFT structures validated through JTAG VIP. The Internal Scan and Scan compression mode of patterns for different faults (transition and stuck at) are generated using ATPG Tetramax tool then simulate it and verified. Simulation of Boundary Scan patterns also done for checking IO pins voltage measurements and the interconnection of the device on board. Some bitmap tests also verified at RTL level and Gate level using inserting DFT which increases Controllability and Observability.