Mixed Signal Validation of Multi Gigabit Serial Interconnect

Abstract

In the past, analog and digital interaction were quite less. Analog designs were verified separately in circuit simulator & digital designs were verified in digital simulator. The interactions between analog and digital were manually checked. As day by day mixed signal designs such as serial interconnect PCIe (Peripheral Component Interconnect Express), DDR, PLL are increasing drastically & exclusively digital models are not found to be sufficient enough, which in turn requires a validation strategy that combines both analog and digital & that can be termed as Mixed Signal Validation.

This report describes Mixed Signal Verification methodology used to validate the design. It also describes System Verilog testbench required to validate various digital blocks with the help of digital simulator & SPICE code to validate analog blocks using fast spice simulator. A validation infrastructure of Multi-Gigabit Serial Interconnect for lane as a DUT is highlighted. Most popular and advance Constrained Random Verification (CRV) methodology, Universal Verification Methodology (UVM) is used to validate the design. Scattering parameter based realistic channel model is used for injection of sequence from stimuli to DUT. Data Checkers are used to verify the correctness of DUT.