Quality Checks And Validation Of Memory Ips

Abstract

SoC designs are becoming more memory dominant. Due to sophisticated design, sensitivity to technology and complicated integration, memory IP needs to be characterized and validated by taking into account reliability issues such as glitches, metastability, timing soft error, noise margin, etc. Reliability-based characterization of memory IP can ensure maximum yield and manufacturability of high performance low power SoC designs. Validation is an enabling methodology for the development of computational models that can be used to make engineering predictions with quantified confidence. Without thorough Validation there are no grounds on which to place confidence in a study results.

The purpose of this report is to give an understanding of how simulation models can be validated. First, validation is defined, including various different forms of validation. Following this there is a description of the linting tool used for the quality check of RTL code. It also includes simulation results for memory IP(ROM). The final part describes basics of synthesis.