Improvements to Intel's Analog IP Design Flows at Sub 32nm or below Process Nodes

Abstract

This project includes studying Intel’s Analog IP Design methodology at 32nm or below process nodes and identifies and implements the opportunities for design flow productivity, stability and quality. Intel's Analog IP design flow is a combination of internal and external design tools and allows users to do top-down analog subsystem design and bottom-up verification of the IP from functional, performance and reliability points of view.

Process variation is the naturally occurring variation the attributes of transistors (length, widths, oxide thickness) when integrated circuits are fabricated. It becomes particularly important at 32nm or below process nodes as the variation becomes a larger percentage of the full length or width of the device. Thus, the design decisions based on the nominal models may not be correct because the models are either overestimations or underestimations of actual values; hence, the resultant circuits may not be optimal. Thus a number of Statistical Simulation Methodologies can be used to analyzing the impact of process variation on typical classes of circuits. The most common methodologies include (i) Monte Carlo (Full MC) (ii) Design of Experiment (Quasi MC) (iii) Most Probable Point (MPP). The Statistical Simulation techniques provide the greatest flexibility for studying the results of process variations. In this project we analyzed impact of random delay variations on 5-stage CMOS inverter chain and random offset variations on 2-stage Operational Amplifier and also find out number of simulations required for particular test cases with compared statistical methodologies.

In 32nm or below process nodes, the reliability effects such as Aging variations (Hot Carrier Instability and Negative Bias Temperature Instability) can significantly alter transistor characteristics, changing circuit performances over the product lifetime. In this project, we simulated PMOS and NMOS transistors were aged with NBTI and HCI degradation due to compare the obtained threshold voltage and drain current shift prediction with the one evaluated based on experimental data. DC and AC NBTI and HCI studied on a single PMOS and NMOS respectively. We demonstrated the AC BTI and HCI stresses in the low to high frequency range on dedicated on-chip CMOS inverter.