Implementation of DFT in Automotive Chip

Abstract

Nowadays, DFT (Design for Testability) is the most essential step in design flow to improve testability of design containing millions of gates. Different DFT techniques like Scan Design, Boundary Scan and BIST (Built-in Self-Test) are used in order to make whole design more controllable and observable. By using DFT in design we can reduce number of test patterns and size of test pattern hence, we can reduce test cost and time to market.

Work in this thesis explain how does scan design work and how it is implemented using DFT Compiler of synopsis in design of SoC of music player. It also explains Memory BIST flow for the same. And at last it explains how patterns are generated for stuck at fault model using ATPG tool (i.e. TETRAMAX). There are 383 patterns are generated for 78850 stuck-at faults. This shows test coverage of 99.56% can be achieved. Hence we can see improvement in testability in terms of test coverage.